Green Communication with Field-programmable Gate Array for Sustainable Development

by Bishwajeet Pandey, Keshav Kumar

The text discusses the designing of field-programmable gate array-based green computing circuits for efficient green communication. It will help senior undergraduate, graduate students, and academic researchers from diverse engineering domains such as electrical, electronics and communication, and computer.

• Discusses hardware description language coding of green communication computing (GCC) circuits
• Presents field-programmable gate arrays-based power-efficient models
• Explores the integrations of universal asynchronous receiver/transmitter and field-programmable gate arrays
• Covers architecture and programming tools of field-programmable gate arrays
• Showcases Verilog and VHDL codes for green computing circuits such as finite impulse response filter, parity checker, and packet counter

The text discusses the designing of energy-efficient network components, using low voltage complementary metal-oxide semiconductors, high-speed transceiver logic, and stub series-terminated logic input/output standards. It showcases how to write Verilog and VHDL codes for green computing circuits including finite impulse response filter, packet counter, and universal asynchronous receiver-transmitter.